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ultra - compact, high - performance drmos device ZSPM9010 datasheet ? 2016 integrated device technology, inc. 1 january 25, 2016 brief description the zspm901 0 drmos is a fully optimized, ultra - compact, inte grated mosfet plus driver power stage solution for high - current, high - frequency, syn - chronous buck dc - dc applications. the ZSPM9010 incorporates a driver ic, two power mosfets, and a bootstrap schottky diode in a thermally enhanced, ultra - compact pqfn40 package (6mmx6mm) . with an integrated approach, the ZSPM9010 ?s com - plete switching powe r stage is optimized for driver and mosfet dynamic performance, system induc - tance, and power mosfet r ds(on) . it uses innova - tive high - performance mosfet technology, which dramatically reduces switch ringing, eliminating the snubber circuit in most buck co nverter applications. an innovative driver ic with reduced dead times and propagation delays further enhances performance. a thermal warning function (thwn) warns of potential over - temperature situations. the ZSPM9010 also incor porates features such as ski p mode (smod) for improved light - load efficiency with a tri - state 3.3v pulse - width modulation (pwm) input for compatibility with a wide range of pwm controllers. the ZSPM9010 drmos is compatible with idt ?s zspm1 000, a leading - edge configur able dig ital power - management system controller for non - isolated point - of - load (pol) supplies. be n efits ? fully optimized system efficiency: >93% peak ? clean switching waveforms with minimal ringing ? 72% space - saving compared to conventional discrete solutions ? optimized f or use with idt ?s zspm1000 true digital pwm controller features ? based on the intel? 4.0 drmos standard ? high - current handling: up to 50 a ? h igh - performance copper - clip package ? tri - s tate 3.3 v pwm input driver ? skip mode (low - side gate turn - off) input (smod#) ? w arning flag for over - temperature conditions ? driver output disable function (disb# pin) ? internal pull - up and pull - down for smod# and disb# inputs, respectively ? i ntegrated schottky d iode technology in the low - side mosfet ? integrated bootstrap schottky diode ? adaptive gate drive timing for shoot - through protection ? under - voltage lockout (uvlo) ? optimized for switching frequencies up to 1mhz available support ? zspm8010 - kit: open - l oop evaluation board for ZSPM9010 physical characteristics ? operation t emperature : - 40 c to + 1 25c ? v in : 3 v to 15v (typical 12 v) ? i out : 40a ( average ), 50a ( maximum ) ? low - profile smd package: 6 mm x6mm pqfn 40 ? idt green packaging and rohs compliant typical applicatio n
ultra - compact, high - performance drmos device ZSPM9010 datasheet ? 2016 integrated device technology, inc. 2 january 25, 2016 typical applications ? telecom switches ? servers and storage ? desktop compute rs ? workstations ? high - performance gaming motherboards ? base stations ? network routers ? industrial applications vdrv vdrv gh d boot gl vcin temp sense 30k 30k gl logic 10a 10a disb# pwm thwn# cgnd smod# pgnd phase vin boot vcin r up_pwm r dn_pwm (q1) hs power mosfet (q2) ls power mosfet gh logic level shift dead time control vswh gl gh input tri-state logic vcin uvlo ZSPM9010 block diagram ordering information product sales code description package ZSPM9010 z a1r ZSPM9010 lead-f ree pqfn40 ? temperature range: - 40c to +125c reel zspm8010 - kit open -l oop evaluation board for ZSPM9010 kit corporate headquarters 6024 silver creek valley road san jose, ca 95138 www.idt.com sales 1- 800- 345- 7015 or 408 - 284- 8200 fax: 408- 284- 2775 www.idt.com/go/sales tech support www.idt.com/go/support disclaimer integrated device technology, inc. (idt) reserves the right to modify the products and/or specifications described herein at any time, without notice, at idt's sole discretion. performance specifications and operating parameters of the described products are determined in an independent state and are not guarante ed to perform th e same way when installed in customer products. the information contained herein is provided without representation or warranty of any kind, whether express or implied, includin g, but not limited to, the suitability of idt's products for any particular pur pose, an implied warranty of merchantability, or non - infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey an y license under intellectual property rights of idt or any third parties. idt 's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health o r safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreeme nt by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the united states and other countries. other trademarks used herein are the property of idt or their respective third party owners. for datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . all contents of this document are copyright of integrated device technology, inc. all rights reserved
ZSPM9010 datasheet ? 2016 integrated device technology, inc. 3 january 25, 2016 contents 1 ic characteristics ............................................................................................................................................. 5 1.1. absolute maximum ratings ....................................................................................................................... 5 1.2. recommended operating conditions ....................................................................................................... 6 1.3. electrical parameters ................................................................................................................................ 6 1. 4. typical performance characteristics ......................................................................................................... 9 2 functional description .................................................................................................................................... 14 2.1. vdrv and disable (disb#) ..................................................................................................................... 15 2.2. thermal warning flag (thwn#) ............................................................................................................. 16 2.3. tri - state pwm input ................................................................................................................................ 16 2.4. adaptive gate drive circuit ..................................................................................................................... 18 2.5. skip mode (smod#) ............................................................................................................................... 18 2.6. p wm ........................................................................................................................................................ 20 3 application design .......................................................................................................................................... 21 3.1. supply capacitor selection ..................................................................................................................... 21 3.2. bootstrap circuit ...................................................................................................................................... 21 3.3. v cin filter ............................................................................................................................................... 21 3.4. power loss and efficiency testing procedures ...................................................................................... 22 4 pin configuration and package ...................................................................................................................... 24 4.1. available packages ................................................................................................................................. 24 4.2. pin description ......................................................................................................................................... 25 4.3. package dimensions ............................................................................................................................... 26 5 circuit board layout considerations .............................................................................................................. 27 6 ordering information ...................................................................................................................................... 28 7 related documents ........................................................................................................................................ 29 8 document revision history ............................................................................................................................ 29 list of figures figure 1.1 safe operating area ........................................................................................................................... 9 figure 1.2 module power loss vs. output current .............................................................................................. 9 figure 1.3 power loss vs. switching frequency ................................................................................................. 9 figure 1.4 power loss vs. input voltage ............................................................................................................. 9 figure 1.5 power loss vs. driver supply voltage ............................................................................................. 10 figure 1.6 power loss vs. output voltage ........................................................................................................ 10 figure 1.7 power loss vs. output inductance ................................................................................................... 10 figure 1.8 driver supply current vs. frequency ............................................................................................... 10 figure 1.9 driver supply current vs. driver supply voltage ............................................................................. 11
ZSPM9010 datasheet ? 2016 integrated device technology, inc. 4 january 25, 2016 figure 1.10 driver supply current vs. output current ......................................................................................... 11 figure 1.11 pwm thresholds vs. driver supply voltage ..................................................................................... 11 figure 1.12 pwm thresholds vs. temperature ................................................................................................... 11 figure 1.13 smod# thresholds vs. driver supply voltage ................................................................................ 12 figure 1.14 smod# thresholds vs. temperature ............................................................................................... 12 figure 1.15 smod# pull - up current vs. temperature ........................................................................................ 12 figure 1.16 disable thresholds vs. driver supply voltage ................................................................................. 12 figure 1.17 disa ble thresholds vs. temperature ................................................................................................ 13 figure 1.18 disable pull - down current vs. temperature .................................................................................... 13 figure 2.1 typical application circuit with pwm control ................................................................................... 14 figure 2.2 ZSPM9010 block diagram ............................................................................................................... 15 figure 2.3 thermal warning flag (thwn) operation ....................................................................................... 16 figure 2.4 pwm and tri - state timing diagram ................................................................................................. 17 figure 2.5 smod# timing diagram ................................................................................................................... 19 figure 2.6 pwm timing ..................................................................................................................................... 20 figure 3.1 power loss measurement block diagram ....................................................................................... 21 figure 3.2 v cin filter block diagram .................................................................................................................. 22 figure 4.1 pin - out pqfn40 package ................................................................................................................ 24 figure 4.2 pqfn40 physical dimensions and recommended footprint .......................................................... 26 figure 5.1 pcb layout example ........................................................................................................................ 28 list of tables table 2.1 uvlo and disable logic .................................................................................................................. 15 table 2.2 smod# logic .................................................................................................................................... 19
ZSPM9010 datasheet ? 2016 integrated device technology, inc. 5 january 25, 2016 1 ic c haracteristics 1.1. absolute maximum ratings the absolute maximum ratings are stress ratings only. the device might not function or be operable above the recommended operating conditions. stresses exceeding the absolute maximum ratings might also damage the device. in addition, extended expo sure to stresses above the recommended operating conditions might affect device reliability. idt does not recommend designing to the ?absolute maximum ratings.? parameter symbol conditions min max units maximum voltage to cgnd ? vcin, vdrv, disb#, pwm, smod#, gl, thwn # pins - 0.3 6.0 v maximum voltage to pgnd or cgnd ? vin pin - 0.3 25.0 v maximum voltage to vswh or phase ? boot, gh pins - 0.3 6.0 v maximum voltage to cgnd ? boot, phase, gh pins - 0.3 25.0 v maximum voltage to cgnd or pgnd ? vswh pin dc o nly - 0.3 25.0 v maximum voltage to pgnd ? vswh pin < 20ns - 8.0 25.0 v maximum voltage to vdrv ? boot pin 22.0 v maximum sink current ? thwn# pin i thwn# - 0.1 7.0 ma maximum average output current 1) i o ut (av) f sw =3 0 0khz, v in =12v, v o ut =1.0v 50 a f sw =1mhz, v in =12v, v o ut =1.0v 45 a junction -to - pcb thermal resistance jpcb 3.5 c/w ambient temperature range t a mb -40 +125 c maximum junction temperature t jmax +150 c storage temperature range t s tor -55 +150 c electrostatic discharge protection esd human body model, jesd22 - a114 2000 v charged device model, jesd22 - c101 1000 v 1) i o ut (av) is rated using a drmos e valuation b oard, t a mb = 25c, natural convection cooling. this rating is limited by the peak drmos temperature, t jmax = 150c, and varies depending on operating conditions, pcb layout , and pcb board to ambient thermal resistance.
ZSPM9010 datasheet ? 2016 integrated device technology, inc. 6 january 25, 2016 1.2. recommended operating conditions the ?recommended operating conditions? table defines the conditions for actual device operation. recom - mended operating conditions are specified to ensure optimal performance to the datasheet specifications. idt does not recommend exceeding them or designing to the ? absolute maximum ratings. ? parameter symbol conditions min typ max units control circuit supply voltage v cin 4.5 5.0 5.5 v gate drive circuit supply voltage v d rv 4.5 5.0 5.5 v output stage supply voltage v i n 3 .0 12.0 15.0 v 1.3. electrical parameters typical values are v in = 12v, v drv = 12v, and t amb = +25c unless otherwise noted. parameter symbol conditions min typ max units basic operation quiescent current i q i q =i vcin+ i v drv , pwm=low or high or f loat 2 ma under - voltage lock - out uvlo threshold uvlo vcin r ising 2.9 3.1 3.3 v uvlo hysteresis uvlo _hyst 0.4 v pwm input pull - up impedance r up_pwm (vcin = vdrv = 5v 10%) 2 6 k pull - down impedance r dn_pwm (vcin = vdrv = 5v 10%) 12 k pwm high - level voltage v ih_pwm (vcin = vdrv = 5v 10%) 1.88 2.25 2.61 v (vcin = vdrv = 5v 5%) 2.00 2.25 2. 50 v tri - state upper threshold v tri_hi (vcin = vdrv = 5v 10%) 1.84 2.20 2.56 v (vcin = vdrv = 5v 5%) 1.94 2.20 2.46 v tri - state lower threshold v tri_lo (vcin = vdrv = 5v 10%) 0.70 0.95 1.19 v (vcin = vdrv = 5v 5%) 0.75 0.95 1.15 v pwm low - level voltage v il_pwm (vcin = vdrv = 5v 10%) 0.62 0 . 85 1.13 v (vcin = vdrv = 5v 5%) 0.66 0 . 85 1.09 v tri -s tate shutoff time t d_hold - off 160 200 ns tri - state open voltage v hiz_pw m (vcin = vdrv = 5v 10%) 1.40 1.60 1.90 v (vcin = vdrv = 5v 5%) 1.45 1.60 1.80 v
ZSPM9010 datasheet ? 2016 integrated device technology, inc. 7 january 25, 2016 parameter symbol conditions min typ max units disb# input high - level input voltage v ih_disb # 2 v low - level input voltage v il_disb # 0.8 v pull - down current i pld 10 a propagation delay disb# , gl transition from high to low t pd_disbl pwm=gnd , lse= 1 25 ns propagation delay disb# , gl transition from low to high t pd_disbh pwm=gnd , lse= 1 25 ns smod# input high - level input voltage v ih_smod # 2 v low - level input voltage v il_smod # 0.8 v pull - up current i plu 10 a propagation delay smod# , gl transition from high to low t pd_slgll pwm=gnd , disb#= 1 10 ns propagation delay smod# , gl transition from low to high t pd_shglh pwm=gnd , disb#= 1 10 ns thermal warning flag activation temperature t act 150 c reset temperature t rst 135 c pull - down resistance r thwn i pld =5ma 30 250ns timeout circuit timeout delay between gh transition from high to low and gl transition f rom low to high t d_timeout sw=0v 250 ns
ZSPM9010 datasheet ? 2016 integrated device technology, inc. 8 january 25, 2016 parameter symbol conditions min typ max units high - side driver output impedance, sourcing r source_gh source current=100ma 1 output impedance, sinking r sink_gh sink current=100ma 0.8 rise time for gh=10% to 90% t r_gh 6 ns fall time for gh=90% to 10% t f_gh 5 ns ls to hs deadband time : gl g oing low to gh g oing high, 1v gl to 10 % gh t d_deadon 10 ns pwm low propagation delay : pwm g oing low to gh g oing low, v il_pwm to 90% gh t pd_plghl 16 30 ns pwm high propagation delay with smod# held low : pwm g oing high to gh g oing high, v ih_pwm to 10% gh t pd_phghh smod# = low 30 ns propagation delay exiting tri -s tate : pwm (from tri -s tate) g oing high to gh g oing high, v ih_pwm to 10% gh t pd_tsghh 30 ns low - side driver output impedance, sourcing r source_gl source current=100ma 1 output impedance, sinking r sink_gl sink current=100ma 0.5 rise time for gl = 10% to 90% t r_gl 20 ns fall time for gl = 90% to 10% t f_gl 13 ns hs to ls deadband time : sw going low to gl going high, 2.2v sw to 10% gl t d_deadoff 12 ns pwm - high propagation d elay : pwm going high to gl going low, v ih_pwm to 90% gl t pd_phgll 9 25 ns propagation delay exiting tri -s tate: pwm (from tri -s tate) going low to gl going high, v il_pwm to 10% gl t pd_tsglh 20 ns boot diode forward - voltage drop v f i f =10ma 0.35 v breakdown voltage v r i r =1ma 22 v
ZSPM9010 datasheet ? 2016 integrated device technology, inc. 9 january 25, 2016 1.4. typical performance characteristics test c onditions: v in =12v, v out =1.0v, v c in =5v, v drv =5v, l out =320nh, t amb =25c, and natural convection cool - ing, unless otherwise specified . figure 1 . 1 safe operating area figure 1 . 2 module power loss vs. output current figure 1 . 3 power loss vs. switching frequency figure 1 . 4 power loss vs. input voltage
ZSPM9010 datasheet ? 2016 integrated device technology, inc. 10 january 25, 2016 figure 1 . 5 power loss vs. driver supply voltage 0.90 0.95 1.00 1.05 1.10 4.50 4.75 5.00 5.25 5.50 normalized module power loss driver supply voltage, v drv and v cin (v) i out = 30a, f sw = 300khz figure 1 . 6 power loss vs. output voltage figure 1 . 7 power loss vs. output inductance 0.98 0.99 1.00 1.01 1.02 1.03 1.04 1.05 1.06 225 275 325 375 425 normalized module power loss output inductance, l out (nh) i out = 30a, f sw = 300khz figure 1 . 8 driver supply current vs. frequency 5 10 15 20 25 30 35 40 45 50 200 300 400 500 600 700 800 900 1000 driver supply current, i vdrv + i vcin (ma) module switching frequency, f sw (khz) i out = 0a
ZSPM9010 datasheet ? 2016 integrated device technology, inc. 11 january 25, 2016 figure 1 . 9 driver supply current vs. driver supply voltage 12 13 14 15 16 17 4.50 4.75 5.00 5.25 5.50 driver supply current , i vdrv + i vcin (ma) driver supply voltage, v drv and v cin (v) i out = 0a, f sw = 300khz figure 1 . 10 driver supply current vs. output current . figure 1 . 11 pwm thresholds vs. driver supply voltage 0.0 0.5 1.0 1.5 2.0 2.5 3.0 4.50 4.75 5.00 5.25 5.50 pwm threshold voltage (v) driver supply voltage, v cin (v) v ih_pwm v hiz_pwm v tri_hi v t ri_lo v il_pwm t a = 25 c figure 1 . 12 pwm thresholds vs. temperature 0.0 0.5 1.0 1.5 2.0 2.5 3.0 - 50 - 25 0 25 50 75 100 125 150 pwm threshold voltage (v) driver ic junction temperature, t j ( o c) v cin = 5v v il_pwm v ih_pwm v tri_hi v t ri_lo
ZSPM9010 datasheet ? 2016 integrated device technology, inc. 12 january 25, 2016 figure 1 . 13 smod# thresholds vs. driver supply voltage 1.2 1.4 1.6 1.8 2.0 2.2 4.50 4.75 5.00 5.25 5.50 smod# threshold voltage (v) driver supply voltage, v cin (v) v ih_smod v il_smod t a = 25 c figure 1 . 14 smod# thresholds vs. temperature 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 - 50 - 25 0 25 50 75 100 125 150 smod threshold voltage (v) driver ic junction temperature ( o c) v ih_smod v cin = 5v v il_smod figure 1 . 15 smod# pull - up current vs. temperature - 12.0 - 11.5 - 11.0 - 10.5 - 10.0 - 9.5 - 9.0 - 50 - 25 0 25 50 75 100 125 150 smod# pull - up current, i plu (ua) driver ic junction temperature, t j ( o c) v cin = 5v figure 1 . 16 disable thresholds vs. driver supply voltage 1.40 1.50 1.60 1.70 1.80 1.90 2.00 - 50 - 25 0 25 50 75 100 125 150 disb threshold voltage (v) driver ic junction temperature, t j ( c) v ih_disb v il_disb v cin = 5v
ZSPM9010 datasheet ? 2016 integrated device technology, inc. 13 january 25, 2016 figure 1 . 17 disable thresholds vs. temperature 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 4.50 4.75 5.00 5.25 5.50 disb# threshold voltage (v) driver supply voltage, v cin (v) v ih_disb t a = 25 o c v il_disb figure 1 . 18 disable pull - down current vs. temperature
ZSPM9010 datasheet ? 2016 integrated device technology, inc. 14 january 25, 2016 2 functional description the ZSPM9010 is a driver - plus - fet module optimized for the synchronous buck converter topology. a single pwm input signal is all that is required to properly drive the high - side and the low - side mosfets. it is capable of driving speeds up to 1mhz. figure 2 . 1 typical application circuit with pwm control vdrv vcin pwm disb# smod# pgnd phase vin boot vswh ZSPM9010 cgnd thwn# c vin pwm control v 5v = 4.5v to 5.5v v in =3v to 15v c vdrv open drain output v out c boot enabled disabled on off l out c out r boot vc in hdrv d boot ldrv (q1) hs power mosfet (q2) ls power mosfet temp sense control cgnd
ZSPM9010 datasheet ? 2016 integrated device technology, inc. 15 january 25, 2016 figure 2 . 2 ZSPM9010 block diagram vdrv vdrv gh d boot gl vcin temp sense 30 k 30 k gl logic 10 a 10 a disb # pwm thwn # cgnd smod # pgnd phase vin boot vcin r up _ pwm r dn _ pwm ( q 1 ) hs power mosfet ( q 2 ) ls power mosfet gh logic level shift dead time control vswh gl gh input tri - state logic vcin uvlo 2.1. vdrv and disable (disb#) the vcin pin is monitored by an under - voltage lockout (uvlo) circuit. when v cin rises above ~ 3.1 v, the driver is enabled. when v cin falls below ~ 2.7 v, the driver is disabled (gh , gl= 0 ; see figure 2 . 2 and section 4.2 ). the driver can also be disabled by pulling the disb# pin low (dis b# < v il_disb ), which holds both gl and gh low regardless of the pwm input state. the driver can be enabled by raising the disb# pin voltage high (disb# > v ih_disb ). table 2 . 1 uvlo and disable logic note: disb# internal pull - down current source is 10 a (typical) . uvlo disb# driver state 0 x disabled (g h =0 , gl=0) 1 0 disabled (g h =0 , gl=0) 1 1 enabled (see table 2 . 2 ) 1 open disabled (g h =0 , gl=0)
ZSPM9010 datasheet ? 2016 integrated device technology, inc. 16 january 25, 2016 activation temperature t j_driveric thermal warning normal operation high low reset temperature voltage at thwn# 135c 150c 2.2. thermal warning flag (thwn#) the ZSPM9010 provides a thermal warning flag (thwn#) to indicate over - temperature conditions. the thermal warning flag uses an o pen - drain output that pulls to cgnd when the activation temperature (150c) is reached. the thwn# output returns to the high - impedance state once the temperature falls to the reset temperature (135c). for use, the thwn# output requires a pull - up resistor, which can be connected to vcin. note that thwn# does not disable the drmos module. figure 2 . 3 thermal warning flag (thwn) operation 2.3. tri - state pwm input the ZSPM9010 incorporates a tri - state 3.3v pwm input gate drive design . the tri - state gate drive has both logic high level and low level, along with a tri - state shutdown voltage window. when the pwm input signal enters and remains within the tri - state voltage window for a defined hold - off time (t d_hold -off ), both gl and gh are pulled low. this feature enables the ga te drive to shut down both high and low side mosfets using only one contro l signal. for example , this can be used for phase shedding in multi - phase voltage regulators. when exiting a valid tri - state condition, the ZSPM9010 follows the pwm input command. if the pwm input goes from tri - state to low, the low - side mosfet is turned o n. if the pwm input goes from tri - state to high, the high - side mosfet is turned on, as illustrated in figure 2 . 4 . the ZSPM9010 ?s design allows for short propagation delays when exiting the tri - state window (see section 1.3 ).
ZSPM9010 datasheet ? 2016 integrated device technology, inc. 17 january 25, 2016 vswh gh to v swh gl 90 % exit 3 - state 1 . 0 v pwm v il _ pw v ih _ pwm v tri _ hi v ih _ pwm v ih _ pwm 1 0 % t hold - off exit 3 - state v ih _ pw m v tri _ h i v tri _ l o v dcm t f _ ghs t r _ gh 1 0 % dcm exit 3 - state 9 0 % 1 0 % 9 0 % enter 3 - state enter 3 - state enter 3 - state v in v out 2 . 2 v enter tri - state exit tri - state enter tri - state exit tri - state exit tri - state enter tri - state v il _ pwm v il _ pwm t pd _ tsglh t hold - off t pd _ tsghh t hold - off t pd _ tsghh ccm t d _ deadoff t d _ deadon t pd _ phgll t pd _ plghl t f _ gh t f _ gl t r _ gl figure 2 . 4 pwm and tri - state timing diagram notes: t pd_xxx = propagation delay from external signal (pwm, smod # , etc.) to ic generated signal; example: t pd_phgll = pwm going high to ls v gs (gl) going low t d_xxx = delay from ic generated signal to ic generated signal; example: t d_deadon = ls v gs low to hs v gs high pwm exiting tri - state t pd_phgll = pwm rise to ls v gs fall, v ih_pw m to 90% ls v gs t pd_tsghh = pwm tri - state to high to hs v gs rise, v ih_pwm to 10% hs v gs t pd_plghl = pwm fall to hs v gs fall, v il_pwm to 90% hs v gs t pd_tsglh = pwm tri - state to low to ls v gs rise, v il_pwm to 10% ls v gs t pd_phghh = pwm rise to hs v gs rise, v ih_pw m to 10% hs v gs (assumes smod held low) smod (see figure 2 . 5 ) dead times t pd_slgll = smod fall to ls v gs fall, 90% to 90% ls v gs t d_deadon = ls v gs fall to hs v gs rise, ls - comp trip value to 10% hs v gs t pd_shglh = smod rise to ls v gs rise, 10% to 10% ls v gs t d_deadoff = vswh fall to ls v gs rise, sw - comp trip value to 10% ls v gs
ZSPM9010 datasheet ? 2016 integrated device technology, inc. 18 january 25, 2016 2.4. adaptive gate drive circuit the low - side driver (gl) is designed to drive a ground - referenced low r ds(on) n - channel mosfet. the bias for gl is internally connected between vdrv and cgnd. when the driver is enabled, the driver's output is 180 out of phase with the pwm input. when th e driver is disabled (disb#=0v), gl is held low. the high - side driver is designed to drive a floating n - channel mosfet. the bias voltage for the high - side driver is developed by a bootstrap supply circuit consisting of the internal schottky diode and exter nal bootstrap capacitor (c boot ). during startup, the vswh pin is held at pgnd, allowing c boot (see section 3.2 ) to charge to v drv through the internal diode. when the pwm input goes high, gh begins to charge the gate of q1, the high - side mosfet. during this transition, the charge is removed from c boot and delivered to the gate of q1. as q1 turns on, v s wh rises to v in , forcing the boot pin to v in + v boot , which provides sufficient v gs enhancement for q1. to complete the switching cycle, q1 is turned off by pulling gh to v s wh . c boot is then recharged to v drv when v s wh falls to pgnd. the gh output is in - phase with the pwm input. the high - side gate is held low when the driver is disabled or the pwm signal is held within the tri - state window for longer than the tri - state hold - off time, t d_hold -off . the driver ic design ensures minimum mosfet dead time while eliminating potential shoot - through (cross - conduction) currents. it senses the state of the mosfets and adjusts the gate drive adaptively to prevent simultaneous conduction. figure 2 . 4 provides the relevant timing waveforms. to prevent overlap during the low - to - high switching transition (q2 off to q1 on), the adaptive circuitry monitors the voltage at the gl pin. when the pwm signal goes high, q2 begins to turn off after a propagation delay (t pd_phgll ). once the gl pin is discharged below ~ 1 v, q1 begins to turn on after adaptive delay t d_deadon . to prevent overlap during the high - to - low transition (q1 off to q2 on), the adaptive circuitry monitors the voltage at the vswh pin. when the pwm signal goes low, q1 begins to turn off after a propagation delay (t pd_plghl ). once the vswh pin falls below approx. 2.2v, q2 begins to turn on after adaptive delay t d_deadoff . v gs(q1) is also monitored. when v gs(q1) is discharged below approx. 1.2v, a secondary adaptive delay is initiated that results in q2 being driven on after t d_timeout , regardless of vswh state. this function is implemented to ensure c boot is recharged each switching cycle in the event that the vswh voltage does not fall below the 2.2v adaptive threshold. secondary delay t d_timeout is longer than t d_deadoff . 2.5. skip mode (smod#) the smod function allows higher converter efficiency under light - load conditions. during smod, the low - side fet gate signal is disabled (held low), preventing discharging of the output capacitors as the filter inductor current attempts reverse current flow ? also known as diode emulation mode . when the smod# pin is pull ed high, the synchronous buck converter works in synchronous mode. this mode allows gating on the low - side fet. when the smod# pin is pulled low, the low - side fet is gated off. see the timing diagram in figure 2 . 5 . if the smod# pin is connected to the pwm controller, the controller can actively enable or disable smod when the controller detects light - load operation .
ZSPM9010 datasheet ? 2016 integrated device technology, inc. 19 january 25, 2016 t d_deadon pwm sw gh to sw gl t pd_phgll t pd_plghl t d_deadoff v ih_ pwm v il_ pwm 90% 1 0% 90% 2.2v 2.2v t pd_phghh t pd_shglh delay from smod# going high to ls v gs high hs turn - on with smod# low smod# t p d _ sl gll delay from smod# going low to ls v gs low dcm ccm ccm 1 0% v ih_ pwm 1 0% v out v ih_ smod v il_ smod 1 0% table 2 . 2 smod# logic note: the smod feature is intended to have a low propagation delay between the smod signal and the low - side fet v gs response time to control diode emulation on a cycle - by - cycle basis. disb# pwm smod# gh gl 0 x x 0 0 1 tri - state x 0 0 1 0 0 0 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 0 figure 2 . 5 smod# timing diagram see figure 2 . 4 for the definitions of the timing parameters.
ZSPM9010 datasheet ? 2016 integrated device technology, inc. 20 january 25, 2016 t d_deadon pwm sw gh to sw gl t pd_phgll t d_deadoff v ih_pwm v il_pwm 9 0% 90% 1 .0v 10% t pd_plghl 2.2v 10% t d_timeout ( 250ns timeout) 1.2v 2.6. pwm figure 2 . 6 pwm timing
ZSPM9010 datasheet ? 2016 integrated device technology, inc. 21 january 25, 2016 vdrv vcin pwm disb # smod # pgnd phase vin boot vswh zspm 9010 thwn # cgnd c vin pwm input v 5 v v in c vdrv v out c boot l out a i 5 v open drain output disb a i in a i out v sw c out r boot on off v 3 application design 3.1. supply capacitor selection for the supply inputs ( vdrv and vcin), a local ceramic bypass capacitor is required to reduce noise and is used to supply the peak transient currents during gate drive switching action . recommendation: use at least a 1f capacitor with an x7r or x5r dielectric . keep this capacitor close to the vcin and vdrv pin s and connect it to the cgnd ground plane with vias. 3.2. bootstrap circuit the bootstrap circuit uses a charge storage capacitor (c boot ), as shown in figure 3 . 1 . a bootstrap capacitance of 100nf x7r or x5r capacitor is typically adequate. a series bootstrap resistor may be needed for specific applications to improve switching noise immunity. the boot resistor may be required when operating near the maximum rated v in and is effective at controlling the high - side mosfet turn - on slew rate and v s wh overshoot. typical r boot values from 0.5 to 2.0 are effective in reducing v s wh overshoot. 3.3. vcin filter the vdrv pin provides power to the gate drive of the high - side and low - side power mosfets. in most cases, vdrv can be connected directly to vcin, which supplies power to the logic circuitry of the gate driver. for additional noise immunity, an rc filter can be inserted between vdrv and vcin. recommen dation: use a 10 resistor (r vcin ) between vdrv and vcin and a 1f capacitor (c vcin ) from vcin to cgnd ( see figure 3 . 2 ). figure 3 . 1 power loss measurement block diagram
ZSPM9010 datasheet ? 2016 integrated device technology, inc. 22 january 25, 2016 ( ) out sw sw i v p ? = ( ) ( ) v 5 v 5 in in in i v i v p ? + ? = ( ) out out out i v p ? = ( ) sw in module _ loss p p p ? = ( ) out in board _ loss p p p ? = vdrv vcin pwm disb# smod# pgnd phase vin boot vswh ZSPM9010 thwn# cgnd c vin pwm input v 5v v in c vdrv v out c boot l out a i 5v open drain output disb a i in a i out v sw c out r boot on off v c vcin r vcin figure 3 . 2 v cin filter block diagram note: blue lines indicate the optional recommended filter. 3.4. power loss and efficiency testing procedures the circuit in figure 3 . 1 has been used to measure power losses. the efficiency has been calculated based on the equations below. power loss calculations: (1) (2) (3) (4) (5)
ZSPM9010 datasheet ? 2016 integrated device technology, inc. 23 january 25, 2016 % p p 100 eff in out board ? ? ? ? ? ? ? ? ? = % p p 100 eff in sw module ? ? ? ? ? ? ? ? ? = efficiency calculations: (6) (7)
ZSPM9010 datasheet ? 2016 integrated device technology, inc. 24 january 25, 2016 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 vswh 43 vin 42 cgnd 41 s m o d # v c i n v d r v b o o t c g n d g h p h a s e n c v i n v i n vin vin vin vin vswh pgnd pgnd pgnd pgnd pgnd v s w h v s w h p g n d p g n d p g n d p g n d p g n d p g n d p g n d p g n d pwm disb # thwn cgnd gl vswh vswh vswh vswh vswh bottom view 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 vswh 43 vin 42 cgnd 41 s m o d # v c i n v d r v b o o t c g n d g h p h a s e n c v i n v i n vin vin vin vin vswh pgnd pgnd pgnd pgnd pgnd v s w h v s w h p g n d p g n d p g n d p g n d p g n d p g n d p g n d p g n d pwm disb # thwn cgnd gl vswh vswh vswh vswh vswh top view 4 pin configuration and package 4.1. available packages the ZSPM9010 is available in a 40 - lead clip - bond pqfn package. the pin - out is shown in figure 4 . 1 . see figure 4 . 2 for the mechanical drawing of the package. figure 4 . 1 pin - out pqfn40 package
ZSPM9010 datasheet ? 2016 integrated device technology, inc. 25 january 25, 2016 4.2. pin description pin name description 1 smod# when smod#=high, the low - side driver is the inverse of pwm input. when smod#=low, the low - side driver is disabled. this pin has a 10a internal pull - up current source. do not add a noise filter capacitor. 2 vcin ic bias supply. a 1 f (minimum) ceramic capacitor is recommended from this pin to cgnd. 3 vdrv power for gate driver. a 1 f (minimum) x5r/x7r ceramic capacitor from this pin to cgnd is recommended. place it as close as possible to this pin . 4 boot bootstrap supply input. provides voltage supply to the high - side mosfet driver. connect a bootstrap capacitor from this pin to phase. 5, 37, 41 cgnd ic ground. ground return for driver ic. 6 gh gate high. for manufacturing test only. this pin must float: it must not be connected . 7 phase switch node pin for bootstrap capacitor routing; electrically shorted to vswh pin. 8 nc no connect ion . the pin is not el ectrically connected internally but can be connected to vin for convenience. 9 - 14, 42 vin input power voltage (o utput stage supply voltage ). 15, 29 - 35, 43 vswh switch node. provides return for high - side bootstrapped driver and acts as a sense point for the adaptive shoot - through protection. 16 ? 28 pgnd power g round (o utput stage ground ) . source pin of the low - side mosfet. 36 gl gate low. for manufacturing test only. this pin must float. it m ust not be connected . 38 thwn# thermal warning flag, open collector output. when temperature exceeds the trip limit, the output is pulled low. thwn# does not disable the module. 39 disb# output disable. when low, this pin disables the p ower mos fet switching (gh and gl are held low). this pin has a 10a internal pull - down current source. do not add a noise filter capacitor. 40 pwm pwm signal input. this pin accepts a tri - state 3.3 v pwm signal from the controller.
ZSPM9010 datasheet ? 2016 integrated device technology, inc. 26 january 25, 2016 bottom view land pattern recommendation notes: unless otherwise specified a) does not fully conform to jedec registration mo - 220, dated may/2005. b) all dimensions are in millimeters. c) dimensions do not include burrs or mold flash. mold flash or burrs does not exceed 0.10mm. d) dimensioning and tolerancing per asme y14.5m - 1994. e) drawing file name: pqfn40arev2 see detail 'a' detail 'a' scale: 2:1 seating plane 0.65 0.40 2.10 0.50 typ 4.50 5.80 2.50 0.25 1.60 0. 60 0.15 2.10 0.35 1 top view front view c 0.30 0.20 0. 05 0.00 1.10 0.90 0.10 c 0.08 c 10 11 20 21 30 31 40 0.40 0.50 (0.70) 0.40 2.000.10 2.000.10 (0.20) (0.20) 1.500.10 0.50 0.30 (4 0x) 0.20 6.00 6.00 0.10 c 2x b a 0.10 c 2x 0.30 0.20 (4 0x) 4.400.10 0.10 c a b 0.05 c (2.20) 0.50 10 1 40 31 30 21 20 11 pin#1 indicator pin #1 indicator 2.400.10 4.3. package dimensions figure 4 . 2 pqfn40 physical dimensions and recommended footprint
ZSPM9010 datasheet ? 2016 integrated device technology, inc. 27 january 25, 2016 5 circuit board layout considerations figure 5 . 1 provides an example of a proper layout for the ZSPM9010 and critical components. all of the high - current paths, such as the v in , v swh , v out , and gnd copper traces , should be short and wide fo r low inductance and resistance. this technique achieves a more stable and evenly distributed current flow, along with enhanced heat radiation and system performance. the following guidelines are recommendations for the printed circuit board (pcb) designer : 1. input ceramic bypass capacitors must be placed close to the vin and pgnd pins. this helps reduce the high - current power loop inductance and the input current ripple induced by the power mosfet switching operation. 2. the v swh copper trace serves two purpose s. in addition to being the high - frequency current path from the drmos package to the output inductor, it also serves as a heat sink for the low - side mosfet in the drmos package. the trace should be short and wide enough to present a low - impedance path for the high - frequency, high - current flow between the drmos and inductor to minimize losses and temperature rise. note that the vswh node is a high - voltage and high - frequency switching node with a high noise potential. care should be taken to minimize couplin g to adjacent traces. since this copper trace also acts as a heat sink for the lower fet, the designer must balance using the largest area possible to improve drmos cooling with maintaining acceptable noise emission. 3. locate the output inductor close to the ZSPM9010 to minimize the power loss due to the vswh copper trace. care should also be taken so the inductor dissipation does not heat the drmos. 4. the power mosfets used in the output stage are effective for minimizing ringing due to fast switching. in most cases, no vswh snubber is required. if a snubber is used, it should be placed close to the vswh and pgnd pins. the resistor and capacitor must be the proper size for the power dissipation. 5. vcin, vdrv, and boot capacitors should be placed as close as possible to the respective pins to ensure clean and stable power. routing width and length should be considered as well. 6. include a trace from phase to vswh to improve the noise margin. keep the trace as short as possible. 7. the layout should include a placeholder to insert a small - value series boot resistor (r boot ) between the boot capacitor (c boot ) and drmos boot pin. the boot - to - vswh loop size, including r boot and c boot , should be as small as possible. the boot r esistor may be required when operating near the maximum rated v in . the boot resistor is effective for controlling the high - side mosfet turn - on slew rate and vswh overshoot. r boot can improve the noise operating margin in synchronous buck designs that might have noise issues due to ground bounce or high positive and negative vswh ringing. however, inserting a boot resistance lowers the drmos efficiency. efficiency versus noise trade - offs must be considered. r boot values from 0.5 to 2.0 are typically effect ive in reducing vswh overshoot. 8. the vin and pgnd pins handle large current transients with frequency components greater than 100mhz. if possible, these pins should be connected directly to the vin and board gnd planes. important: t he use of thermal relief traces in series with these pins is discouraged since this adds inductance to the power path. added inductance in series with the vin or pgnd pin degrades system noise immunity by increasing positive and negative vswh ringing . 9. connect the cgnd pad and pgnd pins to the gnd plane copper with multiple vias for stable grounding. poor grounding can create a noise transient offset voltage level between cgnd and pgnd. this could lead to faulty operation of the gate driver and mosfets.
ZSPM9010 datasheet ? 2016 integrated device technology, inc. 28 january 25, 2016 10. ringing at the boot pin is mo st effectively controlled by close placement of the boot capacitor. do not add a capacitor from boot to ground ; this may lead to excess current flow through the boot diode. 11. the smod# and disb# pins have weak internal pull - up and pull - down current sources, respectively. do not float these pins if avoidable. these pins should not have any noise filter capacitors. 12. use multiple vias on each copper area to interconnect top, inner, and bottom layers to help distribute current flow and heat conduction. vias should be relatively large and of reasonably low inductance. critical high - frequency components, such as r boot , c boot , the rc snubber, and the bypass capacitors should be located as close to the respective drmos module pins as possible on the top layer of the pc b. if this is not feasible, they should be connected from the backside through a network of low - inductance vias. figure 5 . 1 pcb layout example 6 ordering information product sales code description package ZSPM9010 z a1r ZSPM9010 lead - f ree pqfn40 ? temperature range: - 40c to +125c reel zspm8010 - kit open -l oop evaluation board for ZSPM9010 kit top view bottom view
ZSPM9010 datasheet ? 2016 integrated device technology, inc. 29 january 25, 2016 7 related documents document zspm8010 - kit user guide visit idt ?s website www. idt .com or contact your nearest sales office for the latest version of these documents. 8 document revision history revision date description 1.00 february 6 , 201 2 first release 1.01 march 20 , 2012 update to timing diagram figure 2 . 4 . update to block diagram. minor edits to application illustration on page 2. update for i dt contacts. 1.02 august 20, 2 012 update of available support . update of ordering information . update of related documents . 1.03 november 1 9 , 2012 minor edits and update for contact information. 1.04 march 8, 2013 minor updates for cover and header imagery and contact information. january 2 5 , 2016 changed to idt branding. corporate headquarters 6024 silver creek valley road san jose, ca 95138 www.idt.com sales 1- 800- 345- 7015 or 408 - 284- 8200 fax: 408- 284- 2775 www.idt.com/go/sales tech support www.idt.com/go/support disclaimer integrated device technology, inc. (idt) reserves the right to modify the products and/or specifications described herein at any time, without notice, at idt's sole discretion. performance specifications and operating parameters of the described products are determined in an independent state and are not guarante ed to perform th e same way when installed in customer products. the information contained herein is provided without representation or warranty of any kind, whether express or implied, includin g, but not limited to, the suitability of idt's products for any particular pur pose, an implied warranty of merchantability, or non - infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey an y license under intellectual property rights of idt or any third parties. idt 's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health o r safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreeme nt by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the united states and other countries. other trademarks used herein are the property of idt or their respective third party owners. for datasheet type definitions and a glossary of common terms, visit www.i dt.com/go/glossary . all contents of this document are copyright of integrated device technology, inc. all rights reserved

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